The Node-Voltage Method Of Circuit Analysis
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Lab# 1 The Node-Voltage Method of Circuit Analysis
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Abstract
This report used KCL and Ohms law to calculate the node voltages and compare them to the measured node voltages after building the circuit. The calculations were obtained by hand using node analysis. The experiment was simulated on PSpice and the results were verified to hand calculations. The circuit was built in the lab and the results were measured with a digital multi-meter and compared to the calculated values, and the measured percent error in the measurements were found to be within 1 percent error.
1.0 Introduction
Kirchoffs Current Law (KCL), and Ohms law are use to find the three node-voltages, vA, vB, and, vC, of the given circuit (See Figure 1 below). KCL uses node currents and then applies Ohms law to derive an equation in terms of node voltages, resistors, and source voltages. These two laws are only needed when there is: known resistors, and known source voltage. This circuit is a simple circuit because there is only one source voltage and no voltage source shared between two loops.
Figure 1: Circuit Layout
Section 2 goes over the Ohms Law and KCL. Section 3 solves the circuit using calculations by hand and generates equations for needed to solve for node voltages. Section 4 uses PSpice simulation to obtain values of node voltage. Section 5 is the build and measure of the circuit, and percent error comparison. Section 6 is the discussion section of the results, and section 7 is the conclusion of the results.
Linear Circuit Analysis Techniques
This section explains two circuit laws needed to analyze the circuit.
2.1 Ohms Law
Ohms law is used to relate voltage across an element, current through it, and resistance of the element. Ohms law is expressed in (1), where v is voltage across (volts), I is current through (amps), and R is resistance (ohms). The equation follows the passive sign convention.
2.2 Kirchoffs Current Law
Kirchoffs Current Law yields an equation of all currents into and out of a single node. KCL states, the sum of all current into a node equals the sum of all currents leaving a node, shown in (2).
Node-Voltage Analysis
The circuit in Figure 1 was given and elemental voltages and currents were assigned arbitrarily, but satisfying passive sign convention, (elemental current entering into the positive terminal of the elemental voltages), and vD is assigned to the node on the negative side of vs, as a zero voltage reference node, yielding Figure 2 below.
At node A: KCL can be applied yielding
The equation can be rewritten using Ohms Law to
(4)
and then written as .
At node B: KCL can be applied yielding
(6)
The equation can be rewritten using Ohms Law to
and then written as
At node C: KCL can be applied yielding
The equation can be rewritten using Ohms Law to
(10)
and then written as
(11)
The resistors and voltage source used are given below in Table 1.
Table 1: Nominal and Measured Resistor Values
Resistor
Nominal (Ω)
Measured (Ω)
1,000
10,000
9,888
2,200
2,170
3,300
3,275