Computer Architecture
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Describe the basic Von-Neumann architectural definition and describe the limitations imposed by the Von-Neumann bottleneck and how this can be partially overcome
The von Neumann architecture is a model of computing architecture that uses a single storage structure to hold both the set of instructions on how to perform the computation and the data required or generated by the computation. Such machines are also known as stored-program computers. The architecture is named after mathematician John Von Neumann who provided an early written account of a general purpose stored-program computing machine.
By treating the instructions in the same way as the data, a stored-program machine can easily change the instructions. One important motivation for such a facility was the need for a program to increment or otherwise modify the address portion of instructions. This became less important when index registers and indirect addressing became customary features of machine architecture. In other words the machine is reprogrammable.
The separation between the CPU and memory leads to what is known as the von Neumann bottleneck. The bandwidth, or the data transfer rate, between the CPU and memory is very small in comparison with the amount of memory. In modern machines it is also very small in comparison with the rate at which the CPU itself can work. The bottleneck takes place under some circumstances such as, when the CPU is required to perform minimal processing on large amounts of data, which are becoming much more frequent as CPU speeds increase and large amounts of memory become common. This gives rise to a serious limitation in overall effective processing speed, because the CPU is continuously forced to wait for vital data to be transferred to or from memory.
ARM ARCHITECTURE:
ARM stands for Advanced Risc Machines Ltd. ARM were founded in the year 1990 and are owned by Acorn, Apple and VLSI. The original ARM (ARM1, 2 and 3) was a 32 bit CPU, but used 26 bit addressing. The newer ARM6xx spec is completely 32 bits. It has user, supervisor, and various interrupt modes (including 26 bit modes for ARM2 compatibility). ARM is one of the widespread processor cores in the world because of the features like it is one of the most licensed processor; availability of several extensions; and due to low power consumption and reasonable performances it can be used in portable devices.
The various processor cores are ARM 6, ARM 7, ARM 9, ARM 10 and ARM 11. The various extensions are Thumb, EI Segundo, and Jazelle etc.
The ARM architecture has many registers (including user visible PC as R15) with a multiple load/save instruction, though many registers are shadowed in interrupt modes (2 in supervisor and IRQ, 7 in FIRQ) so need not be saved, for fast response. In total there are 37 ARM registers of which the structure depends on the mode of the operation. 16 of 32-bit integer registers R0 – R15 are available in ARM mode. R0 – R12 are general purpose registers; R13 is a stack pointer; R14 is Subroutine Link Register, R15 is a program Counter and R16 is a State Register (CPSR, Current Program Status Register).
To increase the throughput of the system that performs a processing takes without reducing the time taken to process a single item is known as Pipelining. Pipelining has three stages up to ARM 7 processors. Fetch, Decode and Execute are three different stages where fetch stage fetches instruction from memory and copy into the instruction pipeline; In Decode stage the instruction has exclusive control over the decode logic which prepares control signals for the execute cycle. ; In Execute cycle all the essential operations takes place by combinational logic and the cycle duration is long enough to allow the propagation delays. For fetch cycle to execute and for subsequent instructions to be loaded into the pipeline, the PC must “run ahead”. The PC actually points two instructions ahead by the time the execute phase of an instruction is reached hence it contains + 8. The point to the instruction depends upon the exception type.
The concept behind the RISC was developed by John Cocke of IBM Research during 1974. His argument was based upon the notion that a computer uses only 20% of the instructions, making the other 80% superfluous to requirement. A processor based upon this concept would use few instructions, which would require fewer transistors, and make them cheaper to manufacture. By reducing the number of transistors and instructions to only those most frequently used, the computer would get more done in a shorter amount of time.
A feature introduced in microprocessors by the ARM is that every instruction is predicted, using a 4 bit condition code, an idea later used in some HP PA-RISC instructions and the TI 320C6x DSP. Another bit indicates whether the instruction should set condition codes, so intervening instructions dont change them. This easily eliminates many branches and can speed execution. Another unique and useful feature is a barrel shifter which operates on the second operand of most ALU operations, allowing shifts to be combined with most operations (and index registers for addressing), effectively combining two or more instructions into one. These features make ARM code both dense and efficient, despite the relatively low clock rate and short pipeline.
Development of Intel x86 Architecture:
History: The Intel Architecture is evidently todays ideal computer architecture. The development of the Intel Architecture was started in the year 1969, with the development of first processor 8086 in its family followed by many other versions like 8088, 8080 and many more. In the year 1978 the object code program was created for these processors which still executes on the latest versions of the Intel Architecture family.
The 8086 was a 16-bit processor; the architecture remained 16-bit until 1985, when the 32-bit 80386 was developed. Subsequent processors represented refinements of the 32-bit architecture, introducing various extensions, until in 2003 AMD developed a 64-bit extension to the architecture in the form of the AMD64 standard, introduced with the Opteron processor family, which was also adopted a few years later (under a different name) in a new generation of Intel Pentiums.
The manufacturers who have contributed in designing are International Business Machines Corporation (IBM), Advanced Micro Devices (AMD), Pentium and Chips and Technologies, Cyrix, IDT, National Semiconductor and Texas Instruments amongst others.
The Intel architecture which began as 16-bit architecture has reached to