Multicycle Processor
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MULTICYCLE PROCESSOR
Presented by- Akanksha Dixit
Email-id-([email protected])
M.Tech., 3rd SEM ( EMBEDDED SYSTEM & VLSI DESIGN )
Gyan Ganga Institute Of Technology & Sciences
Feb – 2011
ABSTRACT
The purpose of this project is to design a multicycle central processing unit (CPU). The processor will be able to handle fifteen different instructions, including R-type, I-type, and J type. The multicycle implementation breaks instructions down into multiple steps. Each step is designed to take one clock cycle. It allows each functional block to be used more then once per instruction if they are used on different clock cycles. This exercise is done to enhance our understanding of processor design, instruction sets, and Verilog code. The design of this project can be broken down into two diagrams.
One is a block diagram of our design.
The second is the finite state machine that controls the CPU.
Using Verilog Hardware description language. This project deals with the simulation part only.
SINGLE-CYCLE PROCESSOR
A single cycle cpu executes each instruction in one cycle. in other words, one cycle is needed to execute any instruction. in other words, our cpi is 1.Each cycle requires some constant amount of time. this means we will spend the same amount of time to execute every instruction [one cycle], regardless of how complex our instructions may be. to ensure that our processor operates correctly, our slowest instruction must be able to complete execution correctly in one clock tick. this is the big disadvantage of single cycle cpus: the machine must operate at the speed of the slowest instruction. the big advantage of single cycle cpus is that they are easy to implement.
DISADVANTAGES OF SINGLE-CYCLE-PROCESSOR
In modern designs a single cycle implementation of a processor is not used, because it is inefficient. A clock cycle must have the same length for every instruction and therefore it is determined by the longest possible path. Almost this is the path of the load word instruction which uses five functional units in series: the instruction memory, the register file, the ALU, the data memory and the register file again. However a single cycle implementation can be used for a small instruction set. But if the machine gets more powerful there can be used thousands of functional units and then the longest path causes the cycle time
MULTI-CYCLE-PROCESSOR
To avoid the disadvantages of the single cycle implementation described in the section before, a multicycle implementation is used. This technique divides each instruction into steps and each step is executed in one clock
cycle. The multicycle implementation allows a functional unit to be used more than once in a instruction, so that the number of functional units can be reduced. The major advantage of a multicycle design is the ability to share functional units within an execution.
As its name implies, the multiple cycle cpu requires multiple cycles to execute a single instruction. this means that our cpi will be greater than 1.the big advantage of the multi-cycle design is that we can use more or less cycles to execute each instruction, depending on the complexity of the instruction. for example, we can take five cycles to execute a load instruction, but we can take just three cycles to execute a branch instruction. the big disadvantage of the multi-cycle design is increased complexity. Control is now a finite state machine – before it was just combinational logic. another important difference between the single-cycle design and the multi-cycle design is the cycle time. in the single cycle processor, the cycle time was determined by the slowest instruction. in the multi-cycle design, the cycle time is determined by the slowest functional unit [memory, registers, alu]. this greatly reduces our cycle time.
PURPOSE OF MACHINE
This machine is designed to be able execute a variety of instructions in a multicycle implementation. The multicycle implementation breaks instructions down into multiple steps. Each step is designed to take one clock cycle. It allows each functional block to be used more then once per instruction if they are used on different clock cycles. This implementation has several key advantages over a single
cycle implementation. First, it can share modules, allowing the use of fewer hardware components. Instead of multiple arithmetic logic units (ALUs) the multicycle implementation uses only one. Only one memory is used for the data and the instructions also. Breaking complex instructions into steps also allows us to significantly increase the clock cycle because we no longer have to base the clock on the instruction that takes the longest to execute. The multicycle implementation also uses several registers to temporarily hold the output of the previous clock cycle. These include an Instruction register, Memory data register, ALUOut register, etc. The multicycle machine breaks simple instructions down into a series of steps.
These steps typically are the:
1. Instruction fetch step
2. Instruction decode and Register fetch step