Essay About Robust Latches And Ser Increase

Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TETC.2016.2586380, IEEE Transactions on Emerging Topics in ComputingIEEE TRANSACTIONS ON JOURNAL NAME,  MANUSCRIPT ID1Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ RobustnessM. Omaña, T. Edara, C. Metra, Fellow, IEEEAbstract—Analyses recently presented in the literature have shown that the Bias Temperature Instability (BTI) ageing phenomenon may increase significantly the susceptibility to soft errors (SEs) of robust latches. Particularly, this is the case of low-cost robust latches, whose robustness is obtained by increasing the critical charge of their most susceptible node, that is the node most contributing to the latch soft error rate (SER). Therefore, in applications mandating the use of low-cost robust latches, designers will have to face the problem of such latches’ robustness degradation during the IC operation. In order to cope with this problem, we here propose a strategy to reduce the impact of BTI on the SER of standard and low-cost robust latches. It wll be proven that our approach enables to reduce by approximately the 50% the SER increase due to BTI during circuit lifetime with respect to original latches, at limited increase in terms of area overhead, latch setup time and power consumption, and with no impact on the latch input-output delay.Index Terms— Robust Latch; Soft Error; Aging——————————        ◆ ——————————1INTRODUCTIONHE continuous scaling of microelectronic technologySE [9]. Therefore, robust latches in category 2 are less vul-Tenables to keep on increasing system complexity andnerable to SEs than latches in category 1. However, they re-performance. However, this comes together with an in-quire higher area overhead, power consumption and im-creased vulnerability to single event transients (SETs) [1,pact on performance compared to low-cost robust latches2], possibly compromising the system correct operation. Inin category 1.particular, SETs affecting latches and flip-flops are becom-In addition, modern ICs implemented with aggressivelying a major cause of soft errors (SEs) in sequential circuitsscaled technologies are also becoming increasingly prone[3, 4, 5, 6], such as modern high performance microproces-to aging mechanisms, such as bias temperature instabilitysors. Consequently, extensive research efforts have been(BTI) [16, 17]. Negative BTI (NBTI) and Positive BTI (PBTI)devoted to devise hardening approaches for latches andare observed in pMOS and nMOS transistors, respectively.flips-flops.They increase the absolute value of the transistors’ thresh-Robust latches can be grouped in two categories, de-old voltage over time, thus resulting in the degradation ofpending on how their increased robustness against SETs istheir driving strenght.achieved [7]. One category (referred to as category 1) con-As a consequence, in the last few years, together withsists of latches that are made robust by increasing the ca-SET modeling, significant efforts have been devoted alsopacitance  of  some  of  their  nodes  and/or  the  drivingto modeling circuit performance degradation due to BTIstrength of some transistors (e.g., the latches proposed in(e.g., [18, 19, 20, 21, 22]).  Moreover, it has been recently[8, 9, 10, 11, 4]). These approaches usually require low areashown that BTI has also a negative impact on the SE sus-overhead,  but  do  not  guarantee  complete  immunityceptibility of ICs [23, 24, 25]. This because BTI significantlyagainst SEs. In fact, depending on the hitting particle en-reduces the value of the critical charge of ICs’ nodes. Inergy, SETs may still be generated on internal nodes, possi-fact, as shown in [26], the critical charge of a node stronglybly resulting in output SEs. The other category of robustdepends on the value of the restoring current of its pull-latches (referred to as category 2) consists of latches that areup/pull-down networks. Since BTI increases the absolutemade robust by proper modification of their internal struc-value of the transistor threshold voltage over time, it alsoture, making them robust against SEs independently of thereduces the value of the restoring current of the affectedhitting particle energy (e.g., the latches in [12, 13, 5, 14, 7,node. As a result, its critical charge reduces, and the likeli-15]). Consequently, SETs affecting any of the internal orhood of SET generation increases significantly over time.output nodes of these robust latches cannot produce anAs previously mentioned, SETs affecting latches andoutput SE. Only SETs affecting the input node and satisfy-flip-flops are the major cause of SEs in sequential circuits.ing the latch setup and hold times can generate an outputThe impact of BTI on the soft error rate (SER) of a standardlatch and robust latches (of both category 1 and category 2)has been analyzed in [27, 28]. Such analyses showed that————————————————during circuit lifetime, BTI significantly increases the SERof standard latches and low-cost robust latches in category∙M. Omaña and C. Metra are with the University of Bologna (ARCES -DEI), Bologna 40133, Italy. E-mail: {martin.omana; cecilia.metra}@ un-ibo.it. T. Edara was with the same University.